Retirement from Kyoto Institute of Technology (2016.3.)

Year of Birth: 1951

Education: Kyoto University, 1974, Ba.Eng., 1976, Ms.Eng., 1984, Dr.Eng.

Research Fields: Information science, Computer engineering.

Current Research Topics: Computer systems, Computer architectures, Parallel processings, Engineering design education.

Special Lectures:

"What is Engineering Design?" (for students & teachers of engineering colleges or institutes of technology; pdf 220KB, 10p)

Major Publications:

Yamamura, S., Kadota, T., Hirata, H., Niimi, H. and Shibayama, K., Evaluation of a Data Preload Mechanism for a Linked List Structure, Systems and Computers in Japan, Scripta Technica, Vol.33, No.3, pages 21-30 (2002). [ABSTRACT]

Shibayama, K., Yamamoto, M., Hirata, H., Kanoh, Y., Sanetoh, T. and Hagiwara, H., KPR: a Logic Programming Language-Oriented Parallel Machine, Lecture Notes in Computer Science, Vol.315, Springer-Verlag, pages 114-131 (1988). [ABSTRACT]

Tomita, S., Shibayama, K., Nakata, T., Yuasa, S. and Hagiwara, H., A Computer with Low-Level Parallelism -Its Applications to 3-D Graphics and Prolog/Lisp Machines-, 13th Annual Intl. Symp. on Computer Architecture Conf. Proc., IEEE and ACM, pages 280-289 (1986). [ABSTRACT]

Tomita, S., Shibayama, K., Nakata, T. and Hagiwara, H., A User-Microprogrammable, Local Host Computer with Low-Level Parallelism, 10th Annual Intn. Symp. on Computer Architecture Conf. Proc., IEEE and ACM, pages 151-157 (1983).

Shibayama, K., Tomita, S., Hagiwara, H., Yamazaki, K. and Kitamura, T., Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism, Proc. IFIP Congress 80, pages 181-186 (1980).

Academic Activities:

The Institute of Electronics, Information and Communication Engineers, Transactions on Information and Systems, Associate Editor.

ACM Intl. Collegiate Programming Contest, The Kyoto Site of the Asia Programming Contest, Co-Chair.

The Institute of Electronics, Information and Communication Engineers, Computer systems Technical Committee, Chairperson.

Intl. Conference on Fifth Generation Computer Systems, Program board.

Intl. Symposium on Computer Architecture, Program board.

Science Council of Japan, Research Liaison Committee on Computer Science.

Awards:

Information Processing Society of Japan (IPSJ), Information Processing Technology Heritage (2014).

Information Processing Society of Japan (IPSJ), Fellow (2012).

Japanese Society for Engineering Education (JSEE), Annual JSEE Award for Distinguished Author (2009).

Information Processing Society of Japan (IPSJ), Excellent Teaching Tool Developer Award (2009).

The Institute of Electronics, Information and Communication Engineers (IEICE), Annual Distinguished Service Prize to Information and Systems Society Activity (2006).

Information Processing Society of Japan (IPSJ), Annual Best Paper Award (1987).

to Kyoto Institute of Technology, Computer System Laboratory (ARK) (my former laboratory)